1. Field of the Invention
The present invention is generally in the field of microprocessor design and more specifically in the field of microcontroller design and extensions thereto.
2. Description of the Related Art
Certain microprocessors or micro-controllers have been sold in quantities of hundreds of millions. The processors have been available for years, in some cases for decades (8048 since 1976, 8051 since 1980). As a result, tens or hundreds of thousands of programmers have learned the architecture and written programs for the architecture. In addition, sophisticated tools have been designed to facilitate designing with these architectures.
Recently, configurable array technologies have evolved to the point that complete processors can be designed and implemented in a single configurable array, such as an Altera Flex 10K FPGA (Field Programmable Gate Array). In theory, designers can now tailor such popular processor architectures as they wish, by adding features or changing memory size. However, in practice, the task of designing a processor or modifying its architecture is a tremendous task, and generally requires giving up the tools that have been developed for the original (unmodified) architecture. The modified processor is no longer supported by the legacy processor tools and creating a modified processor is complex and time consuming. Moreover, the logic tools needed to design with programmable logic are incompatible with the legacy tools that have evolved to support current processor system architectures such as the one shown in FIG. 1.
What is needed are ways to modify a processing system so that the xe2x80x9clegacyxe2x80x9d tools developed for the unmodified architecture can still be used and so that a configurable subsystem can attach to the processing system to extend the functions of the architecture without involving alterations to the processing system.
The present invention is directed to a method and apparatus that satisfies the above needs. A system in accordance with the present invention includes an central bus for carrying address, data and control signals relating to the address and data on the central bus and an I/O port, connected to the central bus, where the I/O port forms an extended bus having address and data signals and control signals, including a select signal, relating to the address and data signals on the extended bus. The system further includes a functional unit connected to the central bus and having an inexhaustively decoded space, where the use of an unassigned location in the space causes the activation of the select signal on the extended bus. Data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
In one version of the present invention, the functional unit includes an instruction processing unit and a register set residing in the inexhaustively decoded space. Executing an instruction that references an unassigned location in the space causes the activation of the select signal.
In another version of the present invention, the functional unit includes an instruction processing unit for executing instructions residing in the inexhaustively decoded space and the instruction processing unit executes an instruction at an unassigned location in the inexhaustively decoded space to cause the activation of the select signal.
A method in accordance with the present invention includes the steps of: forming an extended bus from an I/O port connected to an central bus of a processing system, where the extended bus includes address data and control signals, including a select signal, relating to the address and data signals on the extended bus; executing an instruction in a functional unit connected to the central bus of the processing system and having an inexhaustively decoded space, where the instruction uses an unassigned location in the inexhaustively decoded space to cause the activation of the select signal on the extended bus; and transferring data between the central bus and the extended bus in response to executing the instruction causing the activation of the select signal.
An advantage of the present invention is that use of legacy tools for the unmodified processing system architecture is preserved because the instruction set activating the select signal is a standard instruction or an additional instruction. In either case, the instruction set and architecture of the unmodified processing system are not altered and existing tools still work with the modified system.
Another advantage is that configurable subsystem is kept separate from the processing system so that the designer has the flexibility to implement extended functions for the processing system independently of the processing system. This advantage is brought about by the extended bus to which the configurable subsystem attaches. The extended bus is designed to easily interface to most, if not all, of the available programmable logic arrays on the market, thereby delivering a great deal of flexibility in designing the configurable subsystems using the logic array vendors"" tools.